A reconfigurable RF sampling receiver for multistandard applications

Anis Latiri, Loïc Joet, Patricia Desgreys, Patrick Loumeau
2006 Comptes rendus. Physique  
Une grande penséeà tous mes amis et compagnons de route, thésards, stagiaires et post-doc avec qui j'ai partagé d'inoubliables moments (je repenseà toutes ces pauses café, matchs de foot du vendredi soir et pizzasà la butte aux cailles) et sur qui je pouvais compterà tout moment. Un grand merci qu'à tous les autres. Je vous suiséternellement reconnaissant pour tous ces petits moments de bonheur. Je remercieégalement Karim Ben Kalaia pour sa gentillesse et pour son précieux coup de main lors de
more » ... e phase d'évaluation du circuit intégré. Je remercie aussi toute ma famille, en particulier mes parents, mes soeurs et mes beaux frères. Leurs encouragements m'ontété d'un grand secours dans les moments difficiles de la thèse. Enfin, un grand mercià ma très chèreépouse Semira pour tout le soutien qu'elle m'a apporté et aussi pour sa patience et sa compréhension pendant les derniers mois de rédaction. Abstract The fast development of wireless communication systems requires more flexible and cost effective radio architectures. A long term goal is the software defined radio, where communication standards are chosen by reconfiguration of hardware. Direct analog to digital conversion of the radio frequency (RF) signal is still unrealistic at present time, due to the high requirements imposed on the analog to digital converter. This motivates the need for a highly flexible RF analog front-end that can be fully integrated in low cost digital deep-submicron CMOS processes. Different techniques for shifting the RF and analog circuit design complexity to digitally intensive domain were developed recently. These techniques are based on direct RF sampling and discrete-time analog signal processing and allow for a great flexibility and reduction of cost and power consumption in a reconfigurable design environment. These concepts have been used in this thesis to develop a reconfigurable discrete-time radio receiver front-end. The circuit, which consists mainly of a transconductance low noise amplifier and two discrete-time analog signal processing stages, performs RF sampling, anti-alias filtering, frequency downconversion, decimation and lowpass filtering. To validate the flexibility and reconfigurability of the receiver, GSM and 802.11g communication standards have been addressed and adopted during system level study. The frequency plan and filtering scheme decided for each standard were made different to fully analyze and validate the flexibility of the architecture. The circuit has been designed in 90nm CMOS technology and first measurement results demonstrated the functionality of the receiver. Additionally, a fully passive 2 nd order discrete-time sinc type anti-alias filter has been described and included in the proposed receiver. Based on capacitive ratios for coefficient weighting, this filter is intended to considerably improve the alias filter rejection, which is one of the major problems reported in present discrete-time receivers. By changing the input sampling rate, the anti-alias filter can be tuned to different RF frequency bands and is hence suitable for true multi-standard operations.
doi:10.1016/j.crhy.2006.07.007 fatcat:7vezilw4rjfhdnemgxjmmounbi