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The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture isdoi:10.1371/journal.pone.0138457 pmid:26491967 pmcid:PMC4619588 fatcat:meb4skql7rewrbgfifsn3sujei