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Implementation of Fast Radix-10 BCD Multiplier in FPGA
2015
Indian Journal of Science and Technology
Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition
doi:10.17485/ijst/2015/v8i19/77160
fatcat:s4c4ikhajjeuremfx2xjl7vyjq