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Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead
2013
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as LDPC codes become very natural alternative options. However, these powerful coding solutions demand soft-decision memory sensing, which results in longer
doi:10.1109/tcsi.2013.2244361
fatcat:4c4h7semn5d5logr5umnaiuvwa