Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead

Guiqiang Dong, Ningde Xie, Tong Zhang
2013 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as LDPC codes become very natural alternative options. However, these powerful coding solutions demand soft-decision memory sensing, which results in longer
more » ... ts in longer on-chip memory sensing latency and memory-to-controller data transfer latency. Leveraging well-established lossless data compression theories, this paper presents several simple design techniques that can reduce such latency penalty caused by soft-decision ECCs. Their effectiveness have been well demonstrated through extensive simulations, and the results suggest that the latency can be reduced by up to 85.3%. Index Terms-LDPC, lossless compression, NAND flash memory, soft sensing. 1549-8328
doi:10.1109/tcsi.2013.2244361 fatcat:4c4h7semn5d5logr5umnaiuvwa