Development of a front end controller/heap manager for PHENIX

M.N. Ericson, M.D. Allen, M.S. Musrock, J.W. Walker, C.L. Brillon, A.L. Wintenberg, G.R. Young
1996 IEEE Nuclear Science Symposium. Conference Record  
A controllerheap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus. a parallel data bus, and a trigger interface. The topology developed is modular so that many
more » ... ar so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented. FIFO3 Available Address FIFO (32x6) C. Address List Manager \Empty Flab The address list provides simultaneous readwrite control, cell write-over protection for both a LVL-I trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, all at a beam crossing rate of 105 ns. Addresses are handled such that up to five LVL-1 events can be maintained in the AMU without write-over. Applicability to multiple detector sub-systems is accomplished
doi:10.1109/nssmic.1996.590892 fatcat:xwmheyqyjbauxl3osv57jjigpa