Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

Jianhong Xiao, Guang Zhang, Tianwei Li, Jose Silva-Martinez
2007 VLSI design (Print)  
A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and
more » ... 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.
doi:10.1155/2007/71974 fatcat:cphpzhgkcfcepbizodd4urfkqu