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Combining compiler and runtime IPC predictions to reduce energy in next generation architectures
Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information directly targeting energy optimizations. As we show in this paper, static information provides some unique benefits, not available with runtime hardware-based techniques alone. To achieve energy reduction, we use IPC information at various granularities, to adaptively adjust voltage and speed, and to throttle the fetchdoi:10.1145/977091.977125 dblp:conf/cf/ChhedaUKKM04 fatcat:uvtrfe22hfe6pkkjg5tmzgtuiq