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This paper proposes the design of a low power Vedic Multiplier using the technique of Vedic Mathematics that has been modified to reduce the power consumption.Vedic multiplier is based on a novel concept in which the partial products are generated using concurrent additions. In this paper an 8 bit Vedic multiplier is designed using four 4 bit Vedic multipliers and various adder circuits. The adder circuits are realized using mux based adders instead of conventional adders as in normal Vedicdoi:10.22214/ijraset.2018.4686 fatcat:xzypjkpcznbrfblpzdd35rucyy