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Embedded systems often involve transmitting feedback signals between multiple control tasks that are implemented on different ECUs communicating via a shared bus. For ensuring stability and control performance, such designs require all control signals to be delivered within a specified deadline, which is ensured through appropriate timing or schedulability analysis. In this paper we study controller design that allows control feedback signals to occasionally miss their deadlines. In particular,doi:10.1145/2647954 fatcat:c7iq4q5nfrfo5kp5gsiyghqvd4