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A design space exploration of transmission-line links for on-chip interconnect
2011
IEEE/ACM International Symposium on Low Power Electronics and Design
With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient. Well-engineered transmission line-based communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level analyses and
doi:10.1109/islped.2011.5993647
fatcat:bhswpy27kzcwnjse77g7nj5m2i