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The implementation of a 2-core multi-threaded itanium-family processor
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an effective 325% increase in MIPS per watt which necessitated a holistic focus on power reduction and management. The next challenge in the implementation was to ensure robust and high frequency circuit operation in the 90-nm process generation which
doi:10.1109/isscc.2005.1493929
fatcat:ssq5v5vcwbak3ackojzzrbqe4y