Low Power Design for Future Wearable and Implantable Devices

Katrine Lundager, Behzad Zeinali, Mohammad Tohidi, Jens Madsen, Farshad Moradi
2016 Journal of Low Power Electronics and Applications  
With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing
more » ... . Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). dynamic power consumption, which means that a great deal of the power spent, is wasted solely on heat generation [1]. This can be dealt with by further researching cooling and packaging in order to avoid overheating the circuits; however, this is an expensive and time limited solution, so this paper addresses methods to generally reduce the overall power consumption of the systems. Since the Internet of Things (IoT) revolution, a new focus has been made on making smart phones, smart watches, tablets etc. even smaller whilst increasing the computation power. And with the recent interest in the Internet of Bio-Nano Things (IoBNT) [2], the focus has moved from just increasing the computation power to also creating extremely compact, ultra low power designs that enable small sensors and actuators to operate independently of wired data connections and external power sources. Especially for implanted sensors, the size restriction is crucial for the bio-compatibility and therefore, it is rarely an option to attach bulk batteries to the implant. Instead they will be powered by scavenging the surroundings for ambient energy. This focus is particularly interesting in the medical field, where a lot of research is dealing with implants and other wearable devices that monitors physical responses from the body. Also sporting equipment has a huge market already, in producing different bio sensors that monitors the physical state of athletes. This development calls for new technologies on several fronts, both on device level and circuitry, systems and applications. To continue and develop more energy efficient systems, device circuit co-design techniques are necessary. As mentioned before, downscaling of component footprint can bring about more compact designs, however to address the rising challenges, new devices such as Multi-Gate Field-Effect Transistors (MuGFETs), Carbon Nanotube FET (CNT-FET), Spin-based FET (Spin-FET) etc. have been proposed. In this article, we will highlight the FinFET device as the most promising alternative and explain the recent strategies to obtain more efficient circuitry in the low power regime, both in digital and analog domain. Furthermore, we will describe techniques to lower the power consumption of a design including digital, analog and memory blocks. In the end, popular energy harvesting methods will be introduced and the possibilities for powering entire low power systems using energy harvesting, will be discussed. The remainder of the paper is organized as follows. Sections 2 and 3 describes the design techniques and challenges in digital and analog domain including a discussion on CMOS and FinFET device characteristics and some basic blocks including memory and amplifiers. In Section 4, the existing energy harvesting techniques for a self-powered battery-less WID is explained in details. In Section 5, the conclusion is drawn.
doi:10.3390/jlpea6040020 fatcat:tf7shjsb25ckjmobfshjrxyqmm