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LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
2007
2007 25th International Conference on Computer Design
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last level cache. However, larger caches threaten to dramatically increase the leakage power as the industry moves into deeper sub-micron technology. In this paper, with the aim of reducing leakage energy we introduce LEMap (Low Energy Map), a novel virtual address translation scheme to control the set of physical pages
doi:10.1109/iccd.2007.4601934
dblp:conf/iccd/ChandarlapatiC07
fatcat:ukqgwk7opfcbzgkj64q32p3dxa