More practical bounded-skew clock routing

Andrew B. Kahng, C.-W. Albert Tsao
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacle-and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments.
more » ... ly, the following issues are addressed: (i) clock routing for varying layer parasitics with nonzero via parasitics; (ii) obstacle-avoidance clock routing; (iii) a new topology design rule for prescribed-delay clock routing; and (iv) predictive modeling of the clock routing itself. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches. Preliminaries Control of signal delay skew has become a dominant objective in the routing of VLSI clock distribution networks; see [13, 9] for reviews. "Exact zero skew" is typically obtained at the expense of increased wiring area and higher power dissipation. In practice, circuits still operate correctly within some nonzero skew bound, hence the actual design requirement is for a bounded-skew routing tree (BST). In our discussion, the distance between two points p and q is the Manhattan (or rectilinear) distance dp; q, and the distance between two sets of points P and Q is dP; Q = minfdp; q j p 2 P and q 2 Qg. The cost of the edge e v is simply its wirelength, denoted je v j; this is always at least as large as the Manhattan distance between the endpoints of the edge, i.e., je v j dlp; lv. Detour wiring, or detouring, occurs when je v j dlp; lv. The cost of T , denoted costT , is the total wirelength of the edges in T . We denote the set of sink locations in a clock routing instance as S = fs 1 ; s 2 ; : : : ; s n g ℜ 2 . A connection topology is a binary tree with n leaves corresponding to the sinks in S. A clock tree T G S is an embedding of the connection topology in the Manhattan plane, i.e., each internal node v 2 G is mapped to a location lv in the Manhattan plane. The root of the clock tree is the source, denoted by s 0 . When the clock tree is rooted at the source, any edge between a parent node p and its child v may be identified with the child node, i.e., we denote this edge as e v . If d i denotes the signal delay from clock source s 0 to sink s i , then the skew of clock tree T is given by skewT = max s i ;s j 2S jd i ,d j j. The BST problem is formally stated as follows. Minimum-Cost Bounded Skew Routing Tree (BST) Problem: Given a set S = fs 1 ; : : : ; s n g R 2 of sink locations and a skew bound B, find a routing topology G and a minimum-cost clock tree T G S that satisfies skewT G S B.
doi:10.1145/266021.266292 dblp:conf/dac/KahngT97 fatcat:4jtho47k4ngfhie2boqsyctkse