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Uncle - An RTL Approach to Asynchronous Design
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems
Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, datapath elements, and finite state machines for controlling datapath sequencing. A commercial synthesis tool is used to produce a gate-level netlist of primitive logic gates and storage elements, which is then transformed into an NCL netlist by the Uncle mappingdoi:10.1109/async.2012.14 dblp:conf/async/ReeseST12 fatcat:sk7pdg2cbfftdknwj2p5m3ngpy