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This paper presents a formal verification for a bit-serial hardware architecture. The developed architecture bases on the combination of different design paradigms and requires sophisticated design optimizations. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, is comprised of synchronous and systematic bit-serial processing operators without a central controlling instance. We add timing constraints at the boundaris of the architecturesdoi:10.1007/978-0-387-72258-0_5 dblp:conf/iess/ZabelRK07 fatcat:bas3osvrejamxdtjt5bbh3f3lq