Approach for a Formal Verification of a Bit-serial Pipelined Architecture [chapter]

Henning Zabel, Achim Rettberg, Alexander Krupp
IFIP – The International Federation for Information Processing  
This paper presents a formal verification for a bit-serial hardware architecture. The developed architecture bases on the combination of different design paradigms and requires sophisticated design optimizations. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, is comprised of synchronous and systematic bit-serial processing operators without a central controlling instance. We add timing constraints at the boundaris of the architectures
more » ... rators. To prove the validity of data synchronization we apply formal verification of the constraints on a cycle accurate representation of the implementation. The results of the formal verification is back annotated to the high-level model. 1.
doi:10.1007/978-0-387-72258-0_5 dblp:conf/iess/ZabelRK07 fatcat:bas3osvrejamxdtjt5bbh3f3lq