An 8×8 nRERL serial multiplier for ultra-low-power aplications

Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-Ik Chae
2000 Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00  
Abstract| An 8 x 8-b nRERL serial multiplier is implemented in a 0.6-m n-well 3-metal CMOS process. nRERL nMOS Reversible Energy Recovery Logic is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultralow-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9 of the energy dissipation of the static CMOS one at the operating frequency 100 kHz at 5V, where its adiabatic and leakage losses were about equal.
doi:10.1145/368434.368497 dblp:conf/aspdac/LimKKC00 fatcat:huao5ubh7bbpbjchzp733bkrdy