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International Journal of Engineering Technology and Applied Science
Full Adder is the heart of any central processing unit that is a core component employed in all the processors. This thesis presents a design methodology using pass transistor logic and transmission gates for the architecture of full adder with minimum number of transistor i.e. reduced size and reduced delay. This is then used to implement a full adder design for carrying out arithmetic and logical tasks. The analysis of the developed full adder design is done at 27°C and 100°C range in CMOS 50fatcat:erbipoggrjgsdjxmgwn3t3q3tu