Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs

Kizheppatt Vipin, Shanker Shreejith, Suhaib A. Fahmy, Arvind Easwaran
<span title="">2014</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tw6bckyjmrhsjj2ya3glampz7u" style="color: black;">2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications</a> </i> &nbsp;
Cyber Physical Systems (CPSs), such as those found in modern vehicles, include a number of important time and safety-critical functions. Traditionally, applications are mapped to several dedicated electronic control units (ECUs), and hence, as new functions are added, compute weight and cost increase considerably. With increasing computational and communication demands, traditional software ECUs fail to offer the required performance to provide determinism and predictability, while multi-core
more &raquo; ... proaches fail to provide sufficient isolation between tasks. Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor. We demonstrate the advantages of such architectures in consolidating distributed processing with predictability, determinism and isolation, enabling ECU consolidation and bandwidth reduction.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/cpsna.2014.14">doi:10.1109/cpsna.2014.14</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/cpsna/VipinSFE14.html">dblp:conf/cpsna/VipinSFE14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yam4aw6hmnaifjjsne3eau4tei">fatcat:yam4aw6hmnaifjjsne3eau4tei</a> </span>
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