AUDIT: Stress Testing the Automatic Way

Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael Schulte, W. Lloyd Bircher, Madhu S. Sibi Govindan
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
is an automation framework for stressmark generation • Target: Multi-core processor • Finding Max. Voltage Droop: Genetic Algorithm with hardware measurement generates effective di/dt stressmarks in a short time • Larger voltage droop than other benchmarks/stressmarks • Higher voltage failure points than other benchmarks/stressmarks works well with different configurations / architectures • Throttling off / on • Different processor Laboratory for Computer Architecture
doi:10.1109/micro.2012.28 dblp:conf/micro/KimJPMSBG12 fatcat:nprlpjid7ff53dvjsaqdicz3au