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AUDIT: Stress Testing the Automatic Way
2012
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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is an automation framework for stressmark generation • Target: Multi-core processor • Finding Max. Voltage Droop: Genetic Algorithm with hardware measurement generates effective di/dt stressmarks in a short time • Larger voltage droop than other benchmarks/stressmarks • Higher voltage failure points than other benchmarks/stressmarks works well with different configurations / architectures • Throttling off / on • Different processor Laboratory for Computer Architecture
doi:10.1109/micro.2012.28
dblp:conf/micro/KimJPMSBG12
fatcat:nprlpjid7ff53dvjsaqdicz3au