A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peakto-peakdoi:10.1109/4.641688 fatcat:c3gwohuzo5efdcz6t43lv6qfnm