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On the performance of LDPC and turbo decoder architectures with unreliable memories
2014 48th Asilomar Conference on Signals, Systems and Computers
In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defectdoi:10.1109/acssc.2014.7094504 dblp:conf/acssc/AndradeVWKBFSC14 fatcat:oacpnurpcnakbclarckm27ai3u