A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2001; you can also visit the original URL.
The file type is
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer can cause processor stalls when it is full, when it contends with a cache miss for access to the next level of the hierarchy, and when it contains the freshest copy of data needed by a load. This paper uses instructionlevel simulation of SPEC92 benchmarks to investigate how different write buffer depths, retirementdoi:10.1109/hpca.1997.569650 dblp:conf/hpca/SkadronC97 fatcat:emcuajahwjcd5du2zxddtytcza