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This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production. The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus.doi:10.23919/date48585.2020.9116506 dblp:conf/date/NoelEKGPCVG20 fatcat:4wcjqljll5bdpdg5mbllcpetdq