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A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
2008
2008 16th International Symposium on Field-Programmable Custom Computing Machines
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We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the 802.16e WiMax standard. The proposed design is fully compliant with all the code classes defined by the standard. It has been validated through an implementation on a Xilinx Virtex5 FPGA component. A four or six-module FPGA design yields a throughput ranging from 10 to 30 Mbit/s by means of 20 iterations at a clock
doi:10.1109/fccm.2008.13
dblp:conf/fccm/CharotWFH08
fatcat:e2hf4mott5c2zabk4htmnnemai