Building a retargetable local instruction scheduler

Vicki Allan, Steven J. Beaty, Bogong Su, Philip H. Sweany
1998 Software, Practice & Experience  
Historically, instruction schedulers have been developed in an ad hoc manner. This paper explores using one scheduler for a number of different architectures and the ramifications of this. In order to achieve this generality, a machine description that encompasses a rich set of architectural features and a scheduler than can accommodate these descriptions are needed. Using the techniques described here, an efficient local instruction scheduler that generates excellent code for instruction-level parallel architectures can be built.
doi:10.1002/(sici)1097-024x(199803)28:3<249::aid-spe152>3.0.co;2-x fatcat:weipmmc6r5ckfoknjpf5syxv7a