Correct-by-construction layout-centric retargeting of large analog designs

Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
<span title="">2004</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 41st annual conference on Design automation - DAC &#39;04</a> </i> &nbsp;
Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance necessitates design reuse with special focus on layout aspects. This paper presents a computer-aided design tool and the methodology for a layoutcentric reuse of large analog intellectual-property blocks. From an existing layout representation, an analog circuit is retargeted to different processes and performances; the
more &raquo; ... corresponding correct-byconstruction layouts are generated automatically and have performances comparable to manually crafted layouts. The tool and the methodology are validated on large analog intellectual-property blocks. While manual re-design and re-layout is known to take weeks to months, our reuse tool-suite achieves comparable performance in hours.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/996566.996609">doi:10.1145/996566.996609</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/BhattacharyaJHS04.html">dblp:conf/dac/BhattacharyaJHS04</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/pjqtd334y5f2jh7z3j6tws7rha">fatcat:pjqtd334y5f2jh7z3j6tws7rha</a> </span>
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