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Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
Reconfigurable architectures have become increasingly important in recent years. In this paper we present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigurable architecture. This mapping scheme considerably reduces the time penalty
doi:10.1145/1016720.1016731
dblp:conf/codes/RiveraSFHB04
fatcat:wul6nkuo5vbi7ofusmmwoolqqe