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The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching activity of the on-chip and off-chip buses at the system-level has been defined to evaluate the power dissipation and to compare the effectiveness of power optimization techniques. The paper aims at providing a framework for architectural exploration of a system design, focusing on the power consumption estimation ofdoi:10.1145/301177.301516 dblp:conf/codes/FornaciariSS99 fatcat:ldx53jxomjeqhguy5a3urxvh24