Hierarchical reconfiguration of FPGAs

Dirk Koch, Christian Beckhoff
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be
more » ... aled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.
doi:10.1109/fpl.2014.6927491 dblp:conf/fpl/KochB14 fatcat:t2q2jjhlgna5zbo7nqgn3vkipq