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Hierarchical reconfiguration of FPGAs
2014
2014 24th International Conference on Field Programmable Logic and Applications (FPL)
Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be
doi:10.1109/fpl.2014.6927491
dblp:conf/fpl/KochB14
fatcat:t2q2jjhlgna5zbo7nqgn3vkipq