A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is application/pdf.
A 32×32-b adiabatic register file with supply clock generator
1998
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A 32 2 32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 m complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the
doi:10.1109/4.668983
fatcat:amcd7mrl7fdoxkz42bifegu4f4