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System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerabledoi:10.11591/ijres.v10.i2.pp77-89 fatcat:g2oumox6sretjodxhph7n3enbe