Formal verification of timed systems: a survey and perspective

Farn Wang
2004 Proceedings of the IEEE  
An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.
doi:10.1109/jproc.2004.831197 fatcat:7e5u5rvdbncqbmkku7szkdyz34