Modular Minicomputers Using Microprocessors

J.A. Arulpragasam, R.A. Giggi, R.F. Lary, D.T. Sullivan, Chin-Chang Wu
1980 IEEE Journal of Solid-State Circuits  
This paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instructions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's.
doi:10.1109/jssc.1980.1051342 fatcat:zhpgfotfq5f4xc7n65lp37zp64