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Masking at Gate Level in the Presence of Glitches
[chapter]
2005
Lecture Notes in Computer Science
It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by "secure" random masking schemes, leak side-channel information, which can be exploited in differential power attacks [14] . The leak is due to the fact that the mathematical models describing the gates neglected multiple switching of the outputs of the gates in a single clock cycle. This effect, however, is typical for CMOS circuits and known as glitching. Hence several
doi:10.1007/11545262_14
fatcat:hbv32qumpvb4zizhkpcpg6ggg4