A High-Throughput FPGA Architecture for Joint Source and Channel Decoding

Matthew F. Brejza, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
<span title="">2017</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding is required by the emerging new video transmission applications, such as the first-person remote control of unmanned vehicles. The recently proposed Unary Error Correction (UEC) code facilitates the Joint
more &raquo; ... e and Channel Coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless channel. In this work, we propose the first hardware implementation of the UEC code that achieves the high processing throughputs as well as ultra-low processing latencies required. This is achieved by extending the application of the recently-proposed Fully Parallel Turbo Decoder (FPTD) from pure stand-alone channel coding to JSCC. This work also proposes several novel improvements to the FPTD, in order to increase its hardware efficiency and supported frame length. We demonstrate the application of these improvements to both the LTE turbo code and the UEC code. We synthesize the proposed fully parallel design on a mid-range FPGA, achieving a throughput of 450 Mbps, as well as a factor of 2.4 hardware efficiency improvement over previous implementations of the FPTD.
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