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Automatic generation of application-specific accelerators for FPGAs from python loop nests
2012
22nd International Conference on Field Programmable Logic and Applications (FPL)
We present Three Fingered Jack, a highly productive approach to mapping vectorizable applications to the FPGA. Our system applies traditional dependence analysis and reordering transformations to a restricted set of Python loop nests. It does this to uncover parallelism and divide computation between multiple parallel processing elements (PEs) that are automatically generated through high-level synthesis of the optimized loop body. Design space exploration on the FPGA proceeds by varying the
doi:10.1109/fpl.2012.6339372
dblp:conf/fpl/SheffieldAK12
fatcat:hphpwnv4uvdkxlwhptkr6p7ery