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Modern applications such as graph and data analytics, when operating on real world data, have working sets much larger than cache capacity and are bottlenecked by DRAM. To make matters worse, DRAM bandwidth is increasing much slower than per CPU core count, while DRAM latency has been virtually stagnant. Parallel applications that are bound by memory bandwidth fail to scale, while applications bound by memory latency draw a small fraction of much-needed bandwidth. While expert programmers maydoi:10.1145/2967938.2967948 dblp:conf/IEEEpact/KirianskyZA16 fatcat:qcyof77l4nfmboitbocuxtamfe