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Efficient power co-estimation techniques for system-on-chip design
2000
Proceedings of the conference on Design, automation and test in Europe - DATE '00
We present efficient power estimation techniques for HW/SW System-On-Chip (SOC) designs. Our techniques are based on concurrent and synchronized execution of multiple power estimators that analyze different parts of the SOC (we refer to this as coestimation), driven by a system-level simulation master. We motivate the need for power co-estimation, and demonstrate that performing independent power estimation for the various system components can lead to significant errors in the power estimates,
doi:10.1145/343647.343691
fatcat:awtvgl3ojzgtfk2l5twpecdwwi