Statistical fault injection for impact-evaluation of timing errors on application performance

Jeremy Constantin, Andreas Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis
2016 Proceedings of the 53rd Annual Design Automation Conference on - DAC '16  
This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circuit structure, hence allowing for a significantly more detailed characterization of application performance under scaled frequency / voltage (including supply noise). The model uses gate level timing statistics extracted by dynamic timing
more » ... dynamic timing analysis from the post place & route netlist of a general-purpose processor to perform instructionaware fault injections. We employ a 28 nm OpenRISC core as a case study, to demonstrate how statistical fault injection provides a more accurate and realistic analysis of power vs. error performance.
doi:10.1145/2897937.2898095 dblp:conf/dac/ConstantinBWCK16 fatcat:kglefiat5nb5bp4g47asf7ttyq