A high-frequency divide-by-256-271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the

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... , it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flipflops is measured in 0.25-lm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.