Sub-5nm All-Around Gate FinFET for Ultimate Scaling

H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. Jeon, G. Lee, J. Oh (+7 others)
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.  
Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO 2 shows an I Dsat of 497µA/µm at V G =V D =1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory.
more » ... urbation theory. And a channel orientation effect, based on a current-flow direction, is shown.
doi:10.1109/vlsit.2006.1705215 fatcat:3zti6w4msrgpthxncxx2tjrzmq