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Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops
2007
2007 Design, Automation & Test in Europe Conference & Exhibition
In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define
doi:10.1109/date.2007.364426
dblp:conf/date/LasbouyguesWAM07
fatcat:45i4c2oexravjomzcohwsqf5sa