Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

B. Lasbouygues, R. Wilson, N. Azemard, P. Maurine
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define
more » ... novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings.
doi:10.1109/date.2007.364426 dblp:conf/date/LasbouyguesWAM07 fatcat:45i4c2oexravjomzcohwsqf5sa