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CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors
2010
2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based on workload requirements. However, accurate allocation of power to these voltage/frequency islands based on time varying workload characteristics as well as controlling the power consumption at the provisioned power level is quite non-trivial. Toward this end, we propose a two-tier feedback-based control theoretic
doi:10.1109/sc.2010.15
dblp:conf/sc/MishraSKD10
fatcat:ovogo5hiozaanofvb7zpx2yi34