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This paper presents the design of a verticallyintegrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32¥32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMDdoi:10.1109/ecctd.2009.5274946 dblp:conf/ecctd/DudekLG09 fatcat:ngxkbbkzo5gpzdqqgc5lt7yin4