A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

Piotr Dudek, Alexey Lopich, Viktor Gruev
2009 2009 European Conference on Circuit Theory and Design  
This paper presents the design of a verticallyintegrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32¥32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMD
more » ... operates in SIMD mode, and processes the image data acquired by the top-layer backside illuminated photosensor circuit. The intra-processor inter-layer communication is achieved by means of throughsilicon vias, and the system is partitioned to minimise the area overhead associated with this communication. The processor comprises 4 analogue and 12 binary registers, and supports arithmetic and logic operations. Various sensor structures have been implemented to evaluate the efficiency of photo-sensing in SOI technology. The prototype circuit measures 2mm¥2mm, with 30μm¥30μm pixel pitch. The architecture and circuit design issues are presented in the paper. I. 978-1-4244-3896-9/09/$25.00 ©2009 IEEE
doi:10.1109/ecctd.2009.5274946 dblp:conf/ecctd/DudekLG09 fatcat:ngxkbbkzo5gpzdqqgc5lt7yin4