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A self-tuning dvs processor using delay-error detection and correction
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.
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In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18µm technology . The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1% targeted error rate at a fixed frequency of 120MHz.
doi:10.1109/vlsic.2005.1469380
fatcat:wrm4ymcqsba6bon57wid47rvse