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Efficient BIST hardware insertion with low test application time for synthesized data paths
1999
Proceedings of the conference on Design, automation and test in Europe - DATE '99
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input
doi:10.1145/307418.307507
fatcat:nt5k77yv4fcazktoibx5h2d4zu