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Design and performance of directory caches for scalable shared memory multiprocessors
1999
Proceedings Fifth International Symposium on High-Performance Computer Architecture
Recent research shows that the occupancy of the coherence controllers is a major performance bottleneck for distributed cache coherent shared memory multiprocessors. A significant part of the occupancy is due to the latency of accessing the directory, which is usually kept in DRAM memory. Most coherence controller designs that use protocol processors for executing the coherence protocol handlers use the data cache of the protocol processor for caching directory entries along with protocol
doi:10.1109/hpca.1999.744354
dblp:conf/hpca/MichaelN99
fatcat:iv7byhxdzvaszlzrno77m24nxu