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Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. Our study leadsdoi:10.1145/360276.360298 dblp:conf/fpga/ChenC01 fatcat:jn7wlf2qgvdcjjg3zqbqajexni