Test vehicle for a wafer-scale field programmable gate array
IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B
Field Programmable Gate Arrays are growing steadily in use and have already change the way designers build digital circuits. With their low cost and very fast turnaround time, they are especially well suited for prototyping new designs. However, the general nature of FPGAs implies a circuit density much lower than custom designs. This currently limits the size of the circuits that can be implemented on a single FPGA to 40000 equivalent gates . Boards of FPGAs are used, but their speed remains
... eir speed remains slow, because of the large capacitance of the inter-chip routing. This thesis investigates the use of Wafer Scale Technology to expand the size of FPGAs to 3 million gates for a 200mrn wafer. The defect avoidance proposed uses the laser link technology to restructure the circuit in a square array. Two different techniques, the row-column substitution and the combination of cell by cell and column substitution, are analyzed. The first one is proposed to increase the yield of small FPGAs while the second one is designed to restructure wafer scale chips. Simulations to show the effect of the restructuring on the chip yield are presented. The proposed design is described and the defect avoidance structures explained in detail. A new kind of device, called the testable laser link, has been designed and tested. Its application in the wafer scale FPGA is presented, both in the power distribution and the reconfiguration. Two chip sized test vehicles incorporating the restructuring devices described in the thesis have been successfully fabricated and the results of different tests of cells and signal routing are analyzed. These indicate that a wafer scale FPGA would be feasible with the described techniques.